1. Field of the Invention
The present invention relates to the field of computers and computer processors, and more particularly to a method and means for allowing a computer to execute instructions as they are received from an external source without first storing said instructions, and an associated method to facilitate communications between computers and the ability of a computer to use the available resources of another computer. The predominant current usage of the present inventive direct execution method and apparatus is in the combination of multiple computers on a single microchip, wherein operating efficiency is important not only because of the desire for increased operating speed but also because of the power savings and heat reduction that are a consequence of the greater efficiency.
2. Description of the Background Art
In the art of computing, processing speed is a much desired quality, and the quest to create faster computers and processors is ongoing. However, it is generally acknowledged in the industry that the limits for increasing the speed in microprocessors are rapidly being approached, at least using presently known technology. Therefore, there is an increasing interest in the use of multiple processors to increase overall computer speed by sharing computer tasks among the processors.
The use of multiple processors creates a need for communication between the processors. Therefore, there is a significant portion of time spent in transferring instructions and data between processors. Each additional instruction that must be executed in order to accomplish this places an incremental delay in the process which, cumulatively, can be very significant. The conventional method for communicating instructions or data from one computer to another involves first storing the data or instruction in the receiving computer and then, subsequently calling it for execution (in the case of an instruction) or for operation thereon (in the case of data).
In the prior art it is known that it is necessary to “get the attention” of a computer from time to time. Even though a computer may be busy with one task, another time-sensitive task requirement can occur that may necessitate temporarily diverting the computer away from the first task. Examples include, but are not limited to, providing input to a computer. In such cases, the computer might need to temporarily acknowledge the input and/or react in accordance with the input. Then, the computer will either continue what it was doing before the input or else change what it was doing based upon the input. Although an external input is used as an example here, the same situation occurs when there is a potential conflict for the attention of the arithmetic logic unit (ALU) between internal aspects of the computer, as well.
When receiving data and changes in status from input/output (I/O) ports, there have been two methods available in the prior art. One has been to “poll” the port, which involves reading the status of the port at fixed intervals to determine whether any data has been received or a change of status has occurred. However, polling the port consumes considerable time and resources. A better alternative has often been the use of “interrupts”. When using interrupts, a processor can go about performing its assigned task and then, when an I/O port/device needs attention or the status changes, it sends an Interrupt Request (IRQ) to the processor. Once the processor receives an Interrupt Request, it will, for example, finish its current instruction, place a few things on the stack, and then execute the appropriate Interrupt Service Routine (ISR). Once the ISR has finished, the processor returns to where it left off. When using this method, the processor doesn't have to waste time, looking to see if the I/O device is in need of attention, but rather the device will only service the interrupt when it needs attention. However, the use of interrupts is far less than desirable in many cases, since there can be a great deal of overhead associated with the use of interrupts. For example, each time an interrupt occurs, a computer may have to temporarily store certain data relating to the task it was previously trying to accomplish, then load data pertaining to the interrupt, and then reload the data necessary for the prior task once the interrupt is handled.
An improvement to the above systems can be found using a system based on the Forth computer language. Forth systems have been able to have more than one “thread” of code executing at one time. This is often called a cooperative round-robin. The order in which the threads get a turn using the central processing unit (CPU) is fixed; for example, thread 4 always gets its turn after thread 3 and before thread 5. Each thread is allowed to keep the CPU as long as it wants to, and then relinquish it voluntarily. The thread does this by calling the word PAUSE. Only a few data items need to be saved during a PAUSE function in order for the original task to be restored, as opposed to large contexts that need to be saved during an interrupt function.
Each thread may or may not have work to do. If task 4 has work to do and the task before it in the round-robin (task 3) calls PAUSE, then task 4 will wake up and work until it decides to PAUSE again. If task 4 has no work to do, it passes control on to task 5. When a task calls a word which will perform an input/output function, and will therefore need to wait for the input/output to finish, a PAUSE is built into the input/output call.
The predictability of PAUSE allows for very efficient code. Frequently, a Forth based cooperative round-robin can give every existing thread a turn at the CPU in less time than it would take a pre-emptive multitasker to decide who should get the CPU next. However, a particular task may tend to overwhelm or overtake the CPU.
Another area of operating efficiency can be found by minimizing leakage current in a computer system. In the quest to make devices smaller, leakage current increases as insulation layers become thinner. In the near future, leakage power could reach as high as 50% of the active power. One attempt to curb leakage current can be found by utilizing sleep transistors. Sleep transistors act like a switch by isolating or disconnecting the power supply and blocks of logic when they are not needed. This can reduce leakage power by a factor of 2-1000 times, as disclosed in an article entitled How to Provide a Power-Efficient Architecture, by Bob Crepps, published in Embedded.com, Jul. 24, 2006.
However, there are several drawbacks in using sleep transistors. Many factors need to be considered in a system in order to incorporate efficient use of these transistors. The threshold voltage of a sleep transistor needs to be large; otherwise, the sleep transistor will have a high leakage current. This requires modification in the complementary metal-oxide semiconductor (CMOS) technology process to support both a high threshold voltage device for the sleep transistor and a low threshold voltage device for the logic gates. In addition, a large sleep transistor increases the area overhead and the dynamic power consumed for turning the transistor on and off.
To guarantee the proper functionality of a circuit, the sleep transistors have to be carefully sized to decrease their voltage drop while they are on. Two gates that switch at different times can share a sleep transistor. However, this is not practical for large circuits. Algorithms are necessary to determine the best implementation of sleep transistors for large circuits.
Other problems associated with sleep transistors include generating noise in the circuits, and a loss of data when used to disconnect flip flops from ground or supply voltage, as disclosed in an article entitled Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits, by Farzan Fallah, et al., published in 2004. A method and/or apparatus is needed to reduce leakage current and provide a more efficient and less problematic computer processor system.